The invention relates to micro-circuits, in general, and more particularly to an improved wafer prealignment system for use in the processing of wafers of silicon and the like to make micro-circuits.
As it is well known by those skilled in the art, for the making of micro-circuits, a wafer of silicon, which may be as large as 120 mm in diameter, for example, must be processed through a number of steps. Included among these steps are steps of dry processing (e.g., an isotopic etching) and steps of fine alignment for exposure purposes. In the case of dry processing, absolute alignment accuracy is not essential. In the case of exposing the wafer, accuracy beyond that obtainable with a prealignment system is necessary. For this purpose, the machines which are used for exposing wafers generally have fine alignment systems. However, for the fine alignment systems to be effective, a prealignment within a certain tolerance, for example, within plus or minus 0.25 mm is necessary to avoid an essentially random search in the fine alignment system. The smaller the prealignment error the better. In other words, with better prealignment, a simpler and faster fine alignment system becomes possible.
Various prior art prealignment systems have been developed. Typically, these handle the wafers by the edges. Handling by the edges is undersirable since it can result in contamination or breakage. Systems which do not touch the edges have been developed. However, they cannot provide the necessary speed, accuracy, and reliability of alignment.
Thus, it is the object of the present invention to provide an improved prealigner and a method of carrying out prealignment which quickly and effectively gives the required accuracy for dry processing and for prealignment in a device where further fine alignment takes place, which does not require handling the edges of the wafer.